Introduction
In VLSI physical design, every stage builds on the previous one — and routing is where the entire circuit finally takes shape as a real, manufacturable layout. After floorplanning, placement, and clock tree synthesis (CTS) are complete, the routing process connects every logic cell, macro, and I/O pin through a precise network of metal wires.
Done well, routing produces a clean layout with minimal wire length, reduced signal delays, and manageable congestion. Done poorly, it introduces short circuits, electromagnetic interference (EMI), and timing violations that can render a chip non-functional.
This article walks through what routing is, why it follows placement and CTS, what inputs it needs, how congestion forms, and what a completed routed netlist represents.
What Is the Routing Process in VLSI?
Routing is the physical design step where interconnecting metal wires are drawn to electrically connect the pins of standard cells, macros, and I/O ports according to the post-CTS netlist. These wires follow specific routing grids defined by the process design kit (PDK) and must satisfy a set of design rule constraints (DRC) mandated by the foundry.
The routing process is split into two main phases:
- Global Routing — Divides the chip area into routing regions (GCells) and assigns nets to paths through those regions without committing to exact wire geometry.
- Detail Routing — Assigns actual metal tracks, vias, and wire widths within each GCell, resolving DRC violations and finalizing the physical layout.
Prerequisites: Why Routing Comes After Placement and CTS
Routing cannot begin until three prior stages are complete. Each provides critical information the router depends on:
| Prior Stage | Information Provided |
|---|---|
| Floorplanning | Die area, macro placement, pin locations |
| Placement | Exact standard cell coordinates |
| Clock Tree Synthesis | Pre-routed clock and reset net paths |
The router must know where every cell and pin sits before it can draw a wire. Clock and reset nets are treated as special nets — they are typically pre-routed or given routing priority so that signal integrity and timing constraints are preserved. The remaining routing resources (metal tracks) are then allocated to data signal nets.
Inputs to the Routing Process
A complete routing run requires the following inputs:
- Post-CTS netlist — Describes all logical connections that must be physically realized
- DEF (Design Exchange Format) file — Contains placement data: cell positions, orientations, and die boundary
- LEF (Library Exchange Format) file — Describes cell abstracts, pin geometries, and routing layer rules
- SDC (Synopsys Design Constraints) — Timing constraints that guide routing priorities
- Technology file / PDK — Metal layer definitions, via rules, spacing, and width constraints
Understanding Congestion in Routing
Congestion is one of the most critical routing challenges. It occurs when the number of nets that need to pass through a specific routing region exceeds the available metal tracks in that region.
Consider a chip with three functional blocks — a memory controller, an ALU, and a peripheral interface — placed adjacent to each other. If the netlist requires 40 signal connections to cross the boundary between the memory controller and the ALU, but only 30 routing tracks exist in that boundary channel, the result is congestion overflow. The router cannot legally complete all connections without violating spacing rules.
Consequences of unresolved congestion:
- Short circuits between adjacent wires
- Increased electromagnetic interference (EMI) and crosstalk
- DRC violations that block tapeout sign-off
- Longer detour routes that increase wire length and degrade timing
Strategies to reduce congestion:
- Spreading cell placement to open routing channels
- Inserting routing blockages over macros
- Using higher metal layers for long global routes
- Re-floorplanning macro placement if hotspot congestion is severe
Objectives of Effective Routing
Routing is not simply about making connections — it is about making optimal connections. The primary objectives are:
- Minimize total wire length — Shorter wires reduce resistive-capacitive (RC) delay, lowering propagation time and improving operating frequency
- Minimize via count — Each via adds resistance; fewer vias improve signal integrity
- Reduce congestion — Distributing wires evenly prevents shorts and EMI
- Meet timing constraints — Critical path nets may need dedicated routing resources or shielding
- Satisfy all DRC rules — Spacing, width, and enclosure rules from the PDK must be met for the chip to be manufacturable
\[ t_{wire} = R \cdot C = \left(\rho \cdot \frac{L}{A}\right) \cdot \left(\varepsilon \cdot \frac{A}{d}\right) \]
Wire delay is directly proportional to length \(L\), which is why minimizing total interconnect length is a core routing objective.
Output: The Routed Netlist and Physical Layout
After routing completion, the design produces a routed DEF file — a geometric description of every wire segment, via, and metal shape on the chip. This file represents the final physical layout before sign-off checks.
The routed layout undergoes:
- DRC (Design Rule Check) — Verifies foundry spacing and width rules
- LVS (Layout vs. Schematic) — Confirms the routed layout matches the original netlist
- STA (Static Timing Analysis) — Validates timing with extracted parasitic RC values from the actual routed wires
Practical Steps in a Typical Routing Flow
- Load post-CTS netlist and DEF into the physical design tool (e.g., Innovus, Fusion Compiler)
- Set routing constraints — Define net priorities, shielding requirements, and layer usage rules
- Run global routing — Analyze congestion maps and adjust placement if necessary
- Run detail routing — Resolve all DRC violations iteratively
- Run post-route optimization — Fix timing, reduce crosstalk, and repair remaining violations
- Extract parasitics (SPEF) — Generate RC models from actual wire geometry
- Run final STA — Confirm timing closure with extracted parasitics
- Run DRC and LVS sign-off — Prepare layout for tapeout submission
Outlook
As process nodes shrink below 5nm, routing complexity grows exponentially. The number of metal layers increases, routing grids become denser, and design rule constraints multiply. AI-assisted routing engines and machine learning-based congestion prediction are becoming standard components of modern EDA flows. Understanding the fundamentals of routing — congestion, wire length optimization, and layer management — remains essential regardless of the tooling, because these principles do not change even as the technology scales.
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