Introduction
Field-programmable gate arrays typically require configuration at every power-up cycle. This characteristic introduces latency and requires dedicated configuration pins. For applications demanding instant operation and permanent programmability, alternative FPGA technologies exist that require configuration only once.
This article examines two permanent programming technologies: antifuse-based and flash-based FPGAs. You will gain an understanding of how antifuse cells are programmed, how flash memory elements retain configuration data, and the architectural differences in logic blocks and interconnect networks between these technologies. The discussion covers programming methods, logic cell structures, and routing architectures used in commercially successful permanently programmed FPGAs.
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What Are Permanently Programmed FPGAs?
Permanently programmed FPGAs use non-volatile configuration technologies that retain their programmed state without external memory or power-up configuration loading. Unlike SRAM-based FPGAs that load configuration data from an external ROM at each startup, these devices are programmed once and maintain that configuration indefinitely.
Two primary technologies enable permanent programming: antifuses and flash memory cells. Antifuse technology creates a permanent conductive path between metal layers when programmed. Flash technology uses floating-gate transistors that store charge to control switching elements. Both approaches eliminate the need for configuration pins and power-up delay.
Antifuse Technology
An antifuse is fabricated as a normally open connection between two metal layers. The structure consists of an insulating material sandwiched between metal lines. In its unprogrammed state, no electrical connection exists.
Programming Mechanism
When a programming voltage is applied across the antifuse terminals, the insulating layer breaks down and forms a permanent conductive link. The resulting connection exhibits resistance of approximately 100 Ω, which is higher than a standard metal via but sufficiently low for signal routing.
Each antifuse must be programmed individually. The FPGA incorporates addressing circuitry that selects specific antifuses and applies the programming voltage. As shown in Figure 3-12, pass transistors connected in parallel with each antifuse allow bypassing during programming. Row and column selection signals activate the appropriate pass transistors, ensuring only the target antifuse receives the programming voltage.
Advantages Over Traditional Fuses
Antifuses offer several benefits compared to conventional fuse technologies. In a typical FPGA, most programmable connections should remain open. Antifuses naturally provide this property—unprogrammed antifuses remain disconnected. A traditional fuse starts as a closed connection that must be blown open, which is inefficient for applications requiring predominantly open connections.
Flash Configuration Technology
Flash memory technology provides non-volatile programmability using floating-gate transistor structures. A floating gate is electrically isolated within the transistor gate stack. A low-leakage capacitor stores charge on this floating gate, and the presence or absence of this charge controls the transistor's switching behavior.
Flash-Programmed Switch Cell
The flash-programmed cell controls two transistors. The first transistor serves as the programmable connection point for interconnect or logic routing. The second transistor provides read-write access to the memory cell. A word line controls access to the floating-gate transistor during programming and read operations.
This architecture allows the FPGA to retain its configuration indefinitely without power, similar to antifuse technology. However, flash-based FPGAs can typically be reprogrammed multiple times, unlike antifuse devices that support only one programming cycle.
Logic Blocks for Permanently Programmed FPGAs
Logic blocks in antifuse-programmed FPGAs rely heavily on multiplexer-based architectures. Multiplexers are well-suited to this technology because their functionality derives from making or breaking connections and routing signals.
Basic Multiplexer Logic Element
A single multiplexer implements a simple logic function. When the control signal a is 0, the output equals input d0. When a is 1, the output equals d1. This element allows configuration of which input signal is copied to the output.
Multilevel Multiplexer Architectures
More complex logic elements use multiple multiplexer stages. A two-level multiplexer structure with four control signals provides significantly richer logic functionality. The control signals for the first-stage multiplexers may be derived from ANDed inputs, while the final stage uses ORed control signals.
Example logic families using these architectures include:
- Actel Axcelerator – Uses C-cells for combinational logic and R-cells for registers, organized into SuperClusters with four C-cells and two R-cells per cluster
- Actel ProASIC 500K – Implements any function of three inputs (except three-input XOR) using multiplexers with true/complement input selection
Interconnection Networks
Interconnect architecture differs between antifuse and flash-based FPGAs. Antifuses introduce less signal degradation than pass transistors used in SRAM-programmable FPGAs, making them attractive for high-performance applications.
Local Wiring Systems
The Actel Axcelerator implements three local wiring systems:
| Wiring System | Function | Performance Characteristic |
|---|---|---|
| FastConnect | Horizontal connections within or between adjacent SuperClusters | Standard programmable routing |
| CarryConnect | Routes carry signals between SuperClusters | Optimized for arithmetic operations |
| DirectConnect | Internal connections between adjacent C-cells and R-cells | No antifuses; lower resistance |
Global Routing
Segmented wiring channels implement generic global routing. Routing tracks span the chip both horizontally and vertically. Segment lengths vary, with most wires divided into segments of different lengths. A small number of wires run the full chip length for long-distance signals.
Three types of global signals are typically provided:
- Hardwired clocks (HCLK) driving R-cell clock inputs directly
- Routed clocks for clock, clear, preset, or enable pins
- Global clear (GCLR) and global preset (GPSET) for R-cells and I/O
Programming Process
Antifuse programming requires applying a voltage sufficient to create the permanent connection. This voltage is delivered through the wires that the antifuse will connect. The FPGA architecture positions all antifuses within interconnect channels, allowing the wiring system to address individual antifuses during programming.
The programming voltage is applied across selected row and column lines. Only the antifuse at the intersection of an activated row and column receives sufficient voltage to program. This addressing scheme, combined with bypass pass transistors, ensures precise control over which antifuse programs.
Outlook
Permanently programmed FPGAs continue to serve applications requiring instant-on operation, high security against configuration readback, and radiation tolerance. Antifuse technology provides superior performance characteristics but supports only one programming cycle. Flash-based devices offer reprogrammability with slightly lower performance but greater flexibility.
As system requirements evolve, hybrid approaches combining embedded flash with antifuse elements may emerge. The fundamental trade-off between programmability and performance remains central to FPGA technology selection for permanent configuration applications.
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